High speed image sensors have been widely used in many applications in different fields including the automotive field, the machine vision field, and the field of professional video photography. The development of high speed image sensors is further driven by the consumer market's continued demand for high speed slow motion video and normal high-definition (HD) video that have a reduced rolling shutter effect.
Complementary metal-oxide semiconductor (“CMOS”) image sensor with backside illumination is dominant in the high-end CMOS sensor market because it can combine high performance with the mature CMOS image sensor process for high volume production. The CMOS image sensor with backside illumination provides the unique advantage of higher sensitivity for better low light performance at high speed (i.e., 16.7 ms for 60 FPS). This advantage makes the CMOS image sensor with backside illumination desirable for video applications that do not include the flash or strobe light that are available in photo applications. The CMOS image sensor with backside illumination also provides more flexibility in the routing on the front-side of the pixel array and a more complex routing can be implemented for better performance.
Current high speed architecture on CMOS image sensors implement a multiple channels, column parallel architecture, in which the frame rate is limited by the row time which is defined as the time it takes for the sensor to readout one row of pixel in the array. This row time limitation creates the bottleneck of high speed image sensor design.
Further, many applications require a high dynamic range (HDR) to capture the scene illuminations ranges from 10−1 for night vision to 105 lux for bright sunlight or direct headlights light condition. This high dynamic range corresponds to a dynamic range of at least 100 dB. Current Charge-coupled devices (CCD) and CMOS sensors cannot achieve this range due to the full well limitation and noise floor limitation, which is typically around 60˜70 dB. A high dynamic range sensor design is needed to extend the applications of CMOS image sensor into the high dynamic range areas.
Column parallel Analog-to-Digital (ADC) architecture has been widely used for its better performance on speed, power and structural noise reduction compared to the global ADC architecture. The column parallel ADC in combination with more advanced CMOS technology provides better power consumption and area efficiency, while providing more complex image processing possibilities.